The present invention relates to an electrically erasable programmable read-only memory (EEPROM). Particularly, this invention relates to a data-reprogramming/retrieval circuit that temporally stores data to be programmed or data to be retrieved for a caching function or a multilevel logical function.
Focused on in the semiconductor industry is reduction of cost per bit for high-capacity flash EEPROMs used as a file memory by miniaturization of cell structure with process techniques and also by multilevel logic techniques for high capacity.
FIG. 42 is a circuit block diagram of a data-reprogramming/retrieval circuit (called a page buffer hereinafter) for a multilevel logical operation (four-level logical operation) to store a 2-bit data in one non-volatile memory cell in a NAND-type flash EEPROM.
The page buffer is provided with a latch 1 connected to a data input/output terminal I/O via a data input/output buffer 50a and a latch 2 that is not directly connected to the buffer 50.
Provided on a bit line BLs connecting the latch 1 and a flash memory cell 5 are transfer transistors 42 and 62. Provided on a bit line BLo connecting the latch 2 and another flash memory cell 5 are transfer transistors 30 and 61.
Transfer transistors 70 and 71, and 80 and 81 are provided on a line carrying Vdd and a line carrying Vss, respectively.
Provided further are transfer transistors 63 and 64 for transferring a pre-charge potential VA and a shield potential VB to the bit lines BLs and BLo, respectively.
The two bit lines BLs and BLo are selectively connected to, or share the page buffer.
Such a page buffer is disclosed in “A Multipage Cell Architecture for High-speed Programming Multilevel NAND Flash Memories”, IEEE J. Solid-State Circuit Circuit, Vol. 33, pages 1228 to 1238, August 1998, K. Takeuchi et al.
Two bits per cell is realized, as illustrated in FIG. 43A in that a relationship between a threshold level distribution for memory cell and 2-bit logic data is defined for allocation of the first and the second bits to different row addresses, thus achieving programming and retrieval of four-level data to and from one memory cell. The first and the second bits are the upper and the lower bits, respectively, of the two bits, such as, “1”, and “0”, respectively, of “10”.
In programming of the second bit-data, data to be programmed and corresponding to the second multilevel row address is loaded into the latch 1 via the data input/output buffer 50.
When the data to be programmed is “0”, programming is performed from a “11”-state to a “10”-state in FIG 43A. On the other hand, when the data to be programmed is “1”, programming is prohibited, so that the “11”-state remains unchanged.
In programming of the first bit-data, as shown in FIG. 44, data to be programmed and corresponding to the first multilevel row address is loaded into the latch 1 via the data input/output buffer 50 while the second bit-data that has been stored in the memory cell 5 is loaded into the latch 2.
When the data to be programmed is “0”, programming is performed from the “1”-state to a “01”-state in FIG. 43A when the second-bit data stored in the latch 2 is “1” whereas from the “10”-state to a “00”-state in FIG. 43A when the second-bit data stored in the latch 2 is “0”.
On the other hand, when the first-bit data stored in the latch 1 is “1”, programming is prohibited, so that the threshold level of the second bit is held as it is and both the “11”-and “10”-states remain unchanged.
In this known structure, a 2-bit logic data is stored in one non-volatile memory cell in which the first-bit data and the second-bit data are handled as data for the first and the second row addresses, respectively, or two addresses (the first and the second row addresses) are allocated for one memory cell.
In retrieval, a word line selection voltage is set in order of Vr00, Vr01 and Vr10, as shown in FIG. 43A.
Data on the voltages Vr00 and Vr01 are loaded into the latches 1 and 2, respectively. Data on the voltage Vr10 is loaded into the latch 1 so that, after the bit line is discharged, it is re-charged or re-discharged with the data in the latches 1 and 2 to meet logically.
Disclosed above is an example of a multilevel logical operation. A page buffer for such an operation, however, requires at least two latches
Not only high capacity for multilevel logical operation, but also enhancement in programming and retrieval speed for flash *EPROM is required, for example, as illustrated in FIG. 45A.
In FIG. 45A, a memory cell 100 is divided into cells 100a and 100b. After data loading for two pages, the data are programmed in the cells 100a and 100b simultaneously to enhance the programming unit for higher effective programming speed. The programming unit is enhanced to four pages, eight pages, and so on, by dividing the memory cell into a 4-divided array, 8-divided array for further higher effective programming speed.
Increase in the number of cell array division, however, takes a long time to load data for each increase in data unit to be programmed. For example, 1-page (512 bytes) and 4-page data loading at 1-byte data input cycle of 50 ns take about 25 μs and 100 μs, respectively. One programming takes about 200 μs.
The effective programming speed is enhanced with four-fold simultaneous programming unit, on the other hand, the next successive 4-page programming has to wail for about 100 μs that corresponds to 4-page data loading.
Moreover, increase in the number of cell array division requires a large chip and causes high consumption of power.
As discussed above, higher capacity and also higher programming speed are expected for flash EEPROMs.
A programming time in multilevel operation is longer several times than that in two-level operation for storing 1-bit data to one non-volatile memory cell. In multilevel operation, a programming time takes long much more than a data load tine, thus increase in data amount to be programmed at once by cell array division serves to enhance an effective programming speed.
Enhancement in effective programming speed only by cell array division takes a long data load time in two-level operation thus inefficient.